This invention relates to network interface integrated circuits for transferring high speed parallel digital data or commands which may be input at variable rates over a single asynchronous high speed serial data link.
Advanced highly parallel distributed data processing architectures rely increasingly on high speed fiber optic links to interconnect processing elements such as computers, signal processors, and sensors. In the past, to achieve high data rates for such interconnects, many parallel links were required. This resulted in increased power consumption and increased size due to the need for many optical transmitters and receivers. An additional problem with such interconnects was that the various elements of the architecture operated at different data rates making it difficult to implement a universal data link. This difficulty resulted because the receiving end of the link and the clock recovery devices usually could not cover a very extended bandwidth. Additionally, attempts were made to develop high speed interface integrated circuits which multiplexed the parallel data onto a serial data link. However, these integrated circuit multiplexers did not achieve the required speeds. Furthermore, this method required several integrated circuits to perform their function resulting in greater size and power consumption.
It is known in the art to provide chip sets which perform several of the required functions. For example, a chip set has been provided for this purpose by Gazelle. However, this chip set has not achieved data rates sufficient for optical interconnects in a computer environment having advanced signal processing equipment. Furthermore, this chip set requires two chips in order to perform both encoder and decoder functions. The Gazelle chip set has a forty bit wide input data word. Therefore this chip set is less suited to sensor or signal processor applications where size is a very important consideration. A Honeywell chip set provided for this purpose offers both a command mode and a data mode with a limited number of word commands. If both modes are provided in an integrated circuit embodiment a more efficient use of space is permitted. Moreover neither chip set offers both an eight bit mode and a sixteen bit mode.